4.5.2 Frontside vs. Backside CCD Performance

**Figure 4.11:** Quantum efficiency comparison between backside illuminated chip (solid line) and frontside illuminated chip (broken line)
$\begin{figure} \centerline{ \psfig {file=ASCdocs/QE_bifi.ps,height=3in,width=4in,angle=270} }\end{figure}$

**Figure 4.12:** Measured and modeled FWHM of frontside illuminated CCDs (solid) and backside illuminated CCDs (broken)
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As previously mentioned, ACIS will employ CCDs in two fundamentally different operating configurations. Some devices will be used with the surface containing the gate structures facing the incident X-ray beam from the HRMA. This is the normal CCD operating configuration, and is called `Frontside Illumination' (FI). Unfortunately the gate structures are required for electrical reasons to have a substantial thickness ( $\sim$ 4000 Å) which leads to a reduction in the low energy quantum efficiency of the device.

An alternative is to remove the substrate silicon from the back of the device, exposing the active sensing volume (the depletion layer) from the back side of the device. This configuration is called `Backside Illumination' (BI). While BI chips have higher low energy quantum efficiency, they have somewhat lower total high energy quantum efficiency due to a lower thickness. More importantly BI chips are harder to make, in that the additional processing required to make a BI chip from a potential FI parent has a loss associated with it, and lab measurements show that BI chips do not approach theoretical energy resolution as the FI chips do.

The advantages of the BI chips are particularly important for applications using the gratings, as the improved quantum efficiency at low energy is very important and the loss of energy resolution is less important because the CCD energy resolution is only used to separate orders, and not measure energy directly. Fig. 4.13 compares the quantum efficiency of BI and FI chips on a wavelength scale (which corresponds to linear spatial location along the grating dispersion direction).

**Figure 4.13:** Quantum efficiency comparison between backside illuminated chip (solid line) and frontside illuminated chip (broken line)
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Fig. 4.14 shows the net effective area of ACIS-S when all CCDs are BI (broken line) and all CCDs are FI (solid line). The gain at energies below 1 keV is dramatic.

**Figure 4.14:** Effective area comparison for ACIS-S with backside illuminated chips (broken line) and frontside illuminated chips (solid line)
$\begin{figure} \centerline{ \psfig {file=ASCdocs/LETG_EffArea_bifi.ps,height=3in,width=4in,angle=270} }\end{figure}$