Field Name |
Length (bits) |
Bit |
Contents |
Description |
Item |
Total |
Algn |
Off |
loadCcBlock |
1632 | 1632 |
16 |
0 |
command Packet |
Load Continuous Clocking Parameter Block (see table 27, swreq Rev. I) |
header |
48 | 48 |
16 |
0 |
command Header |
Command Packet Header |
commandLength |
16 | 16 |
16 |
0 |
uint16 = 102 |
Number of 16-bit words in the command packet |
commandIdentifier |
16 | 16 |
16 |
16 |
uint16 |
Used by ground to identify the command |
commandOpcode |
16 | 16 |
16 |
32 |
uint16 = 10 |
Command Operation code which determines format and action of the command [see enum CmdOpcode]: CMDOP_LOAD_CC |
ccBlockSlotIndex |
16 | 16 |
16 |
48 |
uint16 |
Selects which Continuous Clocking Parameter Block Slot to overwrite with the contained block |
checksum |
16 | 16 |
16 |
64 |
uint16 |
This is the 16-bit XOR checksum value for the following parameter block |
parameterBlockId |
32 | 32 |
16 |
80 |
uint32 |
Identifies the Continuous Clocking Parameter Block |
fepCcdSelect[6] |
4 | 24 |
1 |
112 |
ccd IdSelect |
Array of Ccd Selections indexed by FEP Id [see enum CcdId] |
ccdIdSelection |
4 | 4 |
1 |
112 |
uint4 |
This identifies a CCD, where values 0 through 9 respectively select CCDs I0-I3 and S0-S5, and 10 acts as a deselect. [see enum CcdId] |
fepMode |
4 | 4 |
1 |
136 |
uint4 |
Front End Selection Algorithm (0:Raw, 1:1x3, 2:3x3, 3:15 TBD) [see enum CcdFepMode] |
bepPackingMode |
4 | 4 |
1 |
140 |
uint4 |
Event List Packing Code (0:Faint, 1:Graded, 3:15 TBD) [see enum CcBepMode] |
ignoreBadColumnMap |
1 | 1 |
1 |
144 |
bit |
Disable use of Continuous Clocking Bad Column Map (0:Use, 1:Don't use) |
recomputeBias |
1 | 1 |
1 |
145 |
bit |
Enable bias calibration when used for data run (0: Don't compute, 1:Compute) |
trickleBias |
1 | 1 |
1 |
146 |
bit |
Telemeter re-computed bias (0: Don't send, 1:Send) |
rowSum |
4 | 4 |
1 |
147 |
uint4 |
Number of CCD rows to sum in powers of 2 |
columnSum |
4 | 4 |
1 |
151 |
uint4 |
Number of CCD columns to sum in powers of 2 |
overclockPairsPerNode |
4 | 4 |
1 |
155 |
uint4 |
Number of pairs of (possibly summed) overclock pixels (per output node) |
outputRegisterMode |
2 | 2 |
1 |
159 |
uint2 |
Output Register Mode (0:Full, 1:Diagnostic, 2:AC, 3:BD) [see enum QuadMode] |
ccdVideoResponse[6] |
1 | 6 |
1 |
161 |
video Response |
Array of CCD video responses, indexed by FEP Id. In cases of conflict, the last entry wins. |
videoResponse |
1 | 1 |
1 |
161 |
bit |
This selects the video chain response for a given CCD. 0 indicates 1:1, and 1 indicates a 1:4 response |
fep0EventThreshold[4] |
16 | 64 |
16 |
176 |
int16 |
Threshold set points for each output node coming into Fep 0 [see enum QuadId] |
fep1EventThreshold[4] |
16 | 64 |
16 |
240 |
int16 |
Threshold set points for each output node coming into Fep 1 [see enum QuadId] |
fep2EventThreshold[4] |
16 | 64 |
16 |
304 |
int16 |
Threshold set points for each output node coming into Fep 2 [see enum QuadId] |
fep3EventThreshold[4] |
16 | 64 |
16 |
368 |
int16 |
Threshold set points for each output node coming into Fep 3 [see enum QuadId] |
fep4EventThreshold[4] |
16 | 64 |
16 |
432 |
int16 |
Threshold set points for each output node coming into Fep 4 [see enum QuadId] |
fep5EventThreshold[4] |
16 | 64 |
16 |
496 |
int16 |
Threshold set points for each output node coming into Fep 5 [see enum QuadId] |
fep0SplitThreshold[4] |
16 | 64 |
16 |
560 |
uint16 |
Split Threshold set points for each output node coming into Fep 0 [see enum QuadId] |
fep1SplitThreshold[4] |
16 | 64 |
16 |
624 |
uint16 |
Split Threshold set points for each output node coming into Fep 1 [see enum QuadId] |
fep2SplitThreshold[4] |
16 | 64 |
16 |
688 |
uint16 |
Split Threshold set points for each output node coming into Fep 2 [see enum QuadId] |
fep3SplitThreshold[4] |
16 | 64 |
16 |
752 |
uint16 |
Split Threshold set points for each output node coming into Fep 3 [see enum QuadId] |
fep4SplitThreshold[4] |
16 | 64 |
16 |
816 |
uint16 |
Split Threshold set points for each output node coming into Fep 4 [see enum QuadId] |
fep5SplitThreshold[4] |
16 | 64 |
16 |
880 |
uint16 |
Split Threshold set points for each output node coming into Fep 5 [see enum QuadId] |
lowerEventAmplitude |
16 | 16 |
16 |
944 |
uint16 |
Minimum accepted event amplitude (pulse height filter) |
eventAmplitudeRange |
16 | 16 |
16 |
960 |
uint16 |
Range of event amplitudes accepted by the pulse height filter. |
gradeSelections |
4 | 4 |
1 |
976 |
uint4 |
Bitfield of accepted event grade code flags, indexed by grade code (grade filter) [see Event Grade Code Definition] |
gradeSelectValue |
1 | 1 |
1 |
976 |
bit |
This indicates if events whose grade corresponds to the field should be telemetered. 0 indicates don't send, 1 indicates send [see Event Grade Code Definition] |
windowSlotIndex |
16 | 16 |
16 |
992 |
uint16 |
Slot Id of 1D Window List Parameter Block to use (0xffff selects no windows) |
rawCompressionSlotIndex |
8 | 8 |
16 |
1008 |
uint8 |
Slot identifier of Compression table for raw mode from all FEPs (255 indicates no compression) |
ignoreInitialFrames |
16 | 16 |
16 |
1024 |
uint16 |
The number of whole exposure frames that the FEP is to ignore at the start of a bias calibration. If zero, accept all valid data after the first VSYNC. |
biasAlgorithmId[6] |
8 | 48 |
16 |
1040 |
uint8 |
Selects bias algorithm to use for indexed FEP (0: mean, 1:fractile) [see Bias Algorithm Selection Codes, Continuous Clocking] |
biasRejection[6] |
16 | 96 |
16 |
1088 |
uint16 |
Bias parameter for indexed FEP (mean: sigma rejection, fractile:sorted array index) |
fep0VideoOffset[4] |
16 | 64 |
16 |
1184 |
uint16 |
Video Offset values for each output node coming into FEP 0 [see enum QuadId] |
fep1VideoOffset[4] |
16 | 64 |
16 |
1248 |
uint16 |
Video Offset values for each output node coming into FEP 1 [see enum QuadId] |
fep2VideoOffset[4] |
16 | 64 |
16 |
1312 |
uint16 |
Video Offset values for each output node coming into FEP 2 [see enum QuadId] |
fep3VideoOffset[4] |
16 | 64 |
16 |
1376 |
uint16 |
Video Offset values for each output node coming into FEP 3 [see enum QuadId] |
fep4VideoOffset[4] |
16 | 64 |
16 |
1440 |
uint16 |
Video Offset values for each output node coming into FEP 4 [see enum QuadId] |
fep5VideoOffset[4] |
16 | 64 |
16 |
1504 |
uint16 |
Video Offset values for each output node coming into FEP 5 [see enum QuadId] |
deaLoadOverride |
32 | 32 |
32 |
1568 |
uint32 |
If not zero, pointer to explicit DEA Load in RAM |
fepLoadOverride |
32 | 32 |
32 |
1600 |
uint32 |
If not zero, pointer to explicit FEP Load in RAM |