Flexprint Failure Analysis

The following analysis was provided by Al Pilsbury at MIT/Lincoln Laboratories in response to a series of problems that were traced to the design of the flexprint which connects the individual CCDs to the connectors on the backplate of the detector housing.

Extender Card

An extender board fabricated by Speedy Circuits for a different customer was provided to LL for wire bonding tests. We also subjected it to a series of rapid thermal cycles implemented by dunking it in liquid nitrogen until the boiling stopped. The part was warmed by placing it in front of a hot air stream from a heat gun until the part reached approximately 60 deg C.

This board has lots of acrylic adhesive in it. The copper traces are bonded to the Kapton sheet with acrylic and the various layers are secured with acrylic adhesive.

Our verification of the via integrity was performed by soldering all of the terminals together at one end of the circuit with bus bar. The other end only was dunked and warmed. After every ten cycles the continuity from each surface pad on each side of the circuit was checked to the bus bar at the far end. No effort was made to try to distinguish partial contacts in the vias. There are 69 vias on this board.

We found that after 40 cycles opens began to develop. Testing stopped after a total of 80 thermal cycles at which time we had developed 7 failures. Each failure showed up only on one side i.e. the opposite pad of the same via still made contact with the bus bar.

The failures were spaced uniformly over the 3 x 23 pattern of via pads.

[File 215] shows Failure of via designated "F". Note that there are two failure regions and that they both line up with copper planes. There is some bulging associated with the thick trace that does intercept the via. [File 217] shows a close up of one failure in via F. Note break in layer of gold/nickel.

Uncycled Flex Technologies ACIS Circuit

An unused board from Flex Technologies was sectioned at random vias to establish initial via quality prior to thermal cycling, mounting to alumina, or cleaning at LL. This board had previously been rejected due to insufficient annular rings on the outer layers. This board is serial number 196 from lot 3. Most sections are shown both before and after surface etching. The small numbers on the photos (1 to 5) represent the layer number. Layer 1 is the surface we wire bond to and layer 5 has the cover sheet and is bonded to the alumina substrate.

[File 139 Via "A" 30 X no etch [File 203 Via "A" 30 X with etch
[File 145 Via "A" 100 X, layer 3 to via, no etch [File 207 Via "A" 100 X layer 3 to via, with etch
[File 141 Via "B" 30 X no etch [File 205 Via "B" 30 X with etch
[File 147 Via "B" 100 X, layer 2 to via, no etch [File 209 Via "B" 100 X layer 2 to via, with etch
[File 137 Via "C" 30 X no etch [File 202 Via "C" 30 X with etch
[File 143 Via "C" 100 X, layer 2,4 to via, no etch [File 211 Via "C" 100 X layer 2,4 to via, with etch
[File 135 Via "D" 30 X no etch [File 149 Via "D" 30 X with etch
[File 101 Via "E" 30 X [File 213 Via "F" 200 X layer 5

Thermally Cycled Flex Technologies ACIS Circuit

Six detectors were thermally cycled from -150 to +60 deg C with 1 hour dwells at each extreme temperature and 3 deg C/minute rates between temperatures. A baseline electrical performance was established prior to thermal cycling. After every 10 to 20 thermal cycles the detectors were re characterized (in ambient conditions) to establish their performance. Cycling would then resume in the bell jar operating at pressures typically at 10-7 to 10-8 torr. Shown here are 4 failed vias and one functional via from detector W158C1 after a total of 59 thermal cycles.

[File 127] Via "C" 30X Phase1 to image array via connecting to pin C of connector. Via still functions. Note neck down region. [File 129] Via "C", 100X at neck down region.
[File 105] P3-FS-AB, 30X, Failed via. Layer 5 is to right, layer 1 to left. Electrical testing had established failure between layers 1 and 2 which is seen in photos. [File 117], detail of P3-FS-AB, 100X at failure site.
[File 133], OR-4, 100X. Detail of area between layers 2 and 4. Electrical testing had established open between layers 2 and 4. [File 131], OR-4, 30X.
[File 103], OR-4, 30X. [File 113], 30 X. Solder filled via in connector board. Typical of 4 vias sectioned.